Tag: #gpu-cuda
Writing on GPUs, LLMs, MLOps, Kubernetes — and mindset · 7 posts
Systolic Arrays and Dataflow Architecture — The Heart of the TPU
A deep dive into the systolic array, the structure that lets AI accelerators run matrix multiplication efficiently, complete with ASCII diagrams. We walk through dataflow strategies like weight-stationary and output-stat
2026-06-16 · 20 min read #gpu-cuda#systolic-array#dataflow#tpu#ai-hardwareChiplets and Advanced Packaging — CoWoS, 3D Stacking, and Beyond Moore
A single giant die can no longer push performance higher on its own. This post walks through how chiplets, CoWoS, 3D stacking, and the UCIe standard turned advanced packaging into the variable that decides accelerator pe
2026-06-16 · 27 min read #gpu-cuda#chiplet#advanced-packaging#cowos#ucieAI Interconnect — NVLink, NVSwitch, UALink, and the Art of Scaling Up
In large-scale AI training and inference, the real bottleneck is not compute but communication. This article walks through the principles and practice of AI interconnect — the scale-up domains built by NVLink and NVSwitc
2026-06-16 · 29 min read #gpu-cuda#nvlink#nvswitch#ualink#interconnectPhotonic Computing and Optical Interconnects — Crossing the Memory Wall with Light
In 2026, electrical interconnects have hit the wall of the memory wall and data-movement energy. This post explains how silicon photonics and optical interconnects aim to cross that wall — covering Lightmatter Passage, D
2026-06-16 · 25 min read #gpu-cuda#photonics#silicon-photonics#optical-interconnect#co-packaged-opticsThe AI Semiconductor Supply Chain and Market — Who Actually Makes the Chips (2026)
We trace the value chain behind a single AI chip — design, EDA, IP, foundry, packaging, HBM, and equipment. From TSMC and Samsung to ASML EUV, the CoWoS bottleneck, geopolitics and export controls, the rise of in-house c
2026-06-16 · 19 min read #gpu-cuda#ai-hardware#semiconductor#supply-chain#tsmcGPU Hardware Complete Guide for AI: From Architecture to Selection Criteria
A comprehensive guide to GPU hardware for AI research and training. Covers NVIDIA GPU architectures (Hopper, Blackwell), Tensor Core, NVLink, HBM memory, A100/H100/H200/B200 comparisons, and cloud GPU options in detail.
2026-03-17 · 23 min read #gpu#hardware#nvidia#cuda#gpu-cudaCUDA Programming Complete Guide: GPU Parallel Computing Zero to Hero
A comprehensive guide to mastering CUDA programming from fundamentals to advanced optimization. Covers GPU architecture, kernel writing, memory optimization, mixed precision training, and cuDNN/cuBLAS usage with practica
2026-03-17 · 30 min read #cuda#gpu#gpu-cuda#parallel-computing#nvidia