Blog
Writing on GPUs, LLMs, MLOps, Kubernetes — and mindset · 3517 posts
#2026-03 765#english 592#culture 264#deep-dive 254#kubernetes 247#career 229#ai 216#llm 208#devops 193#2026-04 146#security 141#database 114#observability 113#communication 109#history 107#architecture 100#productivity 96#finance 88#economy 84#mindset 81#psychology 80#ai-papers 79#food 78#it 78#travel 78#deep-learning 77#japanese 77#networking 77#performance 72#business-travel 70#linux 70#gpu 69#ai-agent 66#cs-fundamentals 63#postgresql 60#rag 58#self-improvement 55#learning 53#mlops 53#ai-platform 51
Building FingerScore Hardware 1 — System Design and Bill of Materials (BOM)
This is part one of a hardware series on building the FingerScore ring-shaped score recorder yourself. It walks through translating product requirements into circuits, the system block diagram from sensor to MCU to radio
2026-06-17 · 29 min read #fingerscore#hardware#electronics#ble#embeddedWhy ripgrep Is So Fast
ripgrep beats grep not through magic but through an accumulation of decisions: the Rust regex crate built on finite automata (no backtracking), SIMD-accelerated memchr, parallel directory traversal, respecting .gitignore
2026-06-17 · 12 min read #rust#performance#tools#cliSystolic Arrays and Dataflow Architecture — The Heart of the TPU
A deep dive into the systolic array, the structure that lets AI accelerators run matrix multiplication efficiently, complete with ASCII diagrams. We walk through dataflow strategies like weight-stationary and output-stat
2026-06-16 · 20 min read #gpu-cuda#systolic-array#dataflow#tpu#ai-hardwareMaking Inference Fast — Quantization, Sparsity, and Dataflow from a Hardware Lens
We break down the cost structure of inference through the memory-wall lens, then connect quantization (INT8/FP8/FP4), structured sparsity (2:4), dataflow architectures, operator fusion, batching and KV caching into one p
2026-06-16 · 18 min read #inference#quantization#sparsity#dataflow#gpuGPU vs TPU vs ASIC — The 2026 Inference War
A comparison of the GPU, TPU, and ASIC competition over 2026 inference workloads. We cover Google TPU v6 Trillium and Ironwood, the fast-growing cloud in-house inference ASICs, the throughput/latency/cost/power trade-off
2026-06-16 · 23 min read #gpu#tpu#asic#inference#ai-hardwareCerebras Wafer-Scale Deep Dive — A Whole Model on a Single Chip
A close look at the design of the Cerebras WSE-3, a single chip carved from an entire wafer. We cover the on-chip SRAM-centric structure that routes around the memory wall, the fault-tolerant design, real-time inference
2026-06-16 · 20 min read #cerebras#wafer-scale#ai-hardware#memory-wall#inferencePower and Cooling in the AI Data Center — Infrastructure for the Gigawatt Era
As AI capex explodes and data centers grow to gigawatt scale, power and cooling have emerged as the dominant constraints. We map the big picture: surging rack power density, the limits of air cooling versus direct liquid
2026-06-16 · 21 min read #datacenter#ai-infrastructure#cooling#power#liquid-coolingThe Memory Wall and HBM — The Real Bottleneck That Divides AI Performance
In an era where compute is cheap and data movement is expensive, the real bottleneck of AI performance is memory. From the memory-wall concept to HBM generations, the roofline model and arithmetic intensity, the KV cache
2026-06-16 · 21 min read #memory-wall#hbm#bandwidth#roofline#inferenceGroq and SambaNova — Chips That Went All In on Inference
A deep look at the working principles of two chips that bet everything on inference rather than training: the Groq LPU and the SambaNova RDU. We cover how deterministic execution and compiler scheduling, plus reconfigura
2026-06-16 · 19 min read #groq#sambanova#inference#ai-hardware#lpuChiplets and Advanced Packaging — CoWoS, 3D Stacking, and Beyond Moore
A single giant die can no longer push performance higher on its own. This post walks through how chiplets, CoWoS, 3D stacking, and the UCIe standard turned advanced packaging into the variable that decides accelerator pe
2026-06-16 · 27 min read #gpu-cuda#chiplet#advanced-packaging#cowos#ucieAI Interconnect — NVLink, NVSwitch, UALink, and the Art of Scaling Up
In large-scale AI training and inference, the real bottleneck is not compute but communication. This article walks through the principles and practice of AI interconnect — the scale-up domains built by NVLink and NVSwitc
2026-06-16 · 29 min read #gpu-cuda#nvlink#nvswitch#ualink#interconnectPhotonic Computing and Optical Interconnects — Crossing the Memory Wall with Light
In 2026, electrical interconnects have hit the wall of the memory wall and data-movement energy. This post explains how silicon photonics and optical interconnects aim to cross that wall — covering Lightmatter Passage, D
2026-06-16 · 25 min read #gpu-cuda#photonics#silicon-photonics#optical-interconnect#co-packaged-opticsIn-Memory Computing Principles — Computing Inside the Memory
A deep look at the principles of compute-in-memory (CIM): computing directly inside memory instead of moving data to a compute unit. We cover solving a matrix multiply in one shot with a crossbar array, the difference be
2026-06-16 · 19 min read #in-memory-computing#compute-in-memory#ai-hardware#crossbar#reramEdge AI and the NPU — On-Device Inference Accelerators
We lay out why edge AI runs inference on the device instead of the cloud (latency, privacy, cost) and the concept of the NPU that makes it possible. From Apple Neural Engine, Qualcomm, Edge TPU, and ARM Ethos to model co
2026-06-16 · 22 min read #edge-ai#npu#on-device#inference#quantizationThe AI Semiconductor Supply Chain and Market — Who Actually Makes the Chips (2026)
We trace the value chain behind a single AI chip — design, EDA, IP, foundry, packaging, HBM, and equipment. From TSMC and Samsung to ASML EUV, the CoWoS bottleneck, geopolitics and export controls, the rise of in-house c
2026-06-16 · 19 min read #gpu-cuda#ai-hardware#semiconductor#supply-chain#tsmcThe 2026 AI Accelerator Landscape — From Blackwell to Vera Rubin
A developer-oriented map of the 2026 AI accelerator market. We cover NVIDIA Blackwell and the next-generation Vera Rubin, AMD MI350X, the moment inference capex first overtook training, and how to choose a chip per workl
2026-06-16 · 21 min read #ai-hardware#nvidia-blackwell#vera-rubin#inference#gpuPostgreSQL Version Upgrade Strategies — pg_upgrade and Logical Replication
A practical comparison of three ways to perform a PostgreSQL major version upgrade: dump/restore, pgupgrade, and logical replication. We cover downtime trade-offs, the pgupgrade --link procedure and its caveats, near-zer
2026-06-16 · 16 min read #postgresql#database#upgrade#pg-upgrade#logical-replicationMigration Incident Case Studies and Checklists — Learning from Others Failures
Migrations are among the most common and most painful sources of outages. This article walks through typical failure modes like lock storms, replication lag, data loss, and irreversible changes, derives causes and lesson
2026-06-16 · 14 min read #database#migration#postmortem#incident#reliabilityThe Expand-Contract Pattern — The Right Way to Change Schemas with Zero Downtime
A thorough walkthrough of the Expand-Contract pattern, the standard technique for changing a live database schema without downtime. We cover per-scenario SQL for adding columns, renaming, dropping, and adding constraints
2026-06-16 · 15 min read #database#migration#zero-downtime#expand-contract#reliabilityAWS DMS in Practice — Migration and Continuous Replication (CDC)
A practitioner walkthrough of AWS Database Migration Service from its building blocks to full load and CDC, heterogeneous migration with SCT, LOB handling and data validation, monitoring and cut-over strategy. It also co
2026-06-16 · 19 min read #aws#dms#database#migration#cdc