Tag: #systemverilog

Writing on GPUs, LLMs, MLOps, Kubernetes — and mindset · 2 posts

Open FPGA & RISC-V Development 2026 Deep Dive - Yosys, NextPnR, IceStorm, Lattice ECP5, SiFive, BeagleV-Fire, Tang Nano, PULPino
A 2026 landscape of open FPGA and RISC-V development. With Yosys + NextPnR + IceStorm / Project Trellis / Apicula you can synthesize and place-and-route iCE40, ECP5 and Gowin parts with a fully open toolchain. This guide
2026-05-16 · 35 min read #english #fpga #risc-v #yosys #nextpnr
Hardware HDL & Chip Design 2026 — SystemVerilog / Chisel / SpinalHDL / Amaranth / Yosys / Verilator / TinyTapeout / OpenROAD Deep Dive
The hardware description language (HDL) and chip-design landscape in 2026 is multi-layered. The industry standard is still Verilog/SystemVerilog, but UC Berkeleys Chisel has become the de facto choice for RISC-V cores li
2026-05-16 · 24 min read #hdl #hardware-design #chip-design #verilog #systemverilog

Open FPGA & RISC-V Development 2026 Deep Dive - Yosys, NextPnR, IceStorm, Lattice ECP5, SiFive, BeagleV-Fire, Tang Nano, PULPino