Tag: #microarchitecture
Writing on GPUs, LLMs, MLOps, Kubernetes — and mindset · 1 posts
A Single Instruction Can Take 62 Seconds — Latency Is a Property of the Path, Not of the Instruction
The Assembly Hall of Shame is a leaderboard for the competition to make a single instruction as slow as possible. At the bottom, nop takes 1 cycle; at the top, fxrstor64 takes 198 billion cycles, or 62 seconds. Read that
2026-08-09 · 11 min read #os-concepts#performance#cpu#microarchitecture#benchmark